quartus - Running timing simulation in modelsim -

i try simulate very simple .vo file,the output of quartus compilation, attached code, .v file , quartus output .vo file. simulating modelsim-altera used. after trying running simulation following error appeared on screen. how can fix this?

thanks

ca.v :

module ca (input , b, output c);     assign c = + b; endmodule 

ca.vo :

// copyright (c) 1991-2014 altera corporation. rights reserved. // use of altera corporation's design tools, logic functions  // , other software , tools, , ampp partner logic  // functions, , output files of foregoing  // (including device programming or simulation files), ,  // associated documentation or information expressly subject  // terms , conditions of altera program license  // subscription agreement, altera quartus ii license agreement, // altera megacore function license agreement, or other  // applicable license agreement, including, without limitation,  // use sole purpose of programming logic  // devices manufactured altera , sold altera or  // authorized distributors.  please refer applicable  // agreement further details.  // vendor "altera" // program "quartus ii 64-bit" // version "version 14.0.0 build 200 06/17/2014 sj full version"  // date "12/16/2014 07:07:50"  //  // device: altera ep4ce6e22c8 package tqfp144 //   //  // verilog file should used modelsim-altera (verilog) //   `timescale 1 ps/ 1 ps  module ca (     a,     b,     c); input   a; input   b; output  c;  // design ports information // c    =>  location: pin_30,    i/o standard: 2.5 v,    current strength: default //    =>  location: pin_31,    i/o standard: 2.5 v,    current strength: default // b    =>  location: pin_32,    i/o standard: 2.5 v,    current strength: default   wire gnd; wire vcc; wire unknown;  assign gnd = 1'b0; assign vcc = 1'b1; assign unknown = 1'bx;  tri1 devclrn; tri1 devpor; tri1 devoe; // synopsys translate_off initial $sdf_annotate("ca_v.sdo"); // synopsys translate_on  wire \c~output_o ; wire \b~input_o ; wire \a~input_o ; wire \add0~0_combout ;   // location: ioobuf_x0_y8_n16 cycloneive_io_obuf \c~output (     .i(\add0~0_combout ),     .oe(vcc),     .seriesterminationcontrol(16'b0000000000000000),     .devoe(devoe),     .o(\c~output_o ),     .obar()); // synopsys translate_off defparam \c~output .bus_hold = "false"; defparam \c~output .open_drain_output = "false"; // synopsys translate_on  // location: ioibuf_x0_y6_n15 cycloneive_io_ibuf \b~input (     .i(b),     .ibar(gnd),     .o(\b~input_o )); // synopsys translate_off defparam \b~input .bus_hold = "false"; defparam \b~input .simulate_z_as = "z"; // synopsys translate_on  // location: ioibuf_x0_y7_n1 cycloneive_io_ibuf \a~input (     .i(a),     .ibar(gnd),     .o(\a~input_o )); // synopsys translate_off defparam \a~input .bus_hold = "false"; defparam \a~input .simulate_z_as = "z"; // synopsys translate_on  // location: lccomb_x1_y7_n0 cycloneive_lcell_comb \add0~0 ( // equation(s): // \add0~0_combout  = \b~input_o  $ (\a~input_o )      .dataa(\b~input_o ),     .datab(gnd),     .datac(gnd),     .datad(\a~input_o ),     .cin(gnd),     .combout(\add0~0_combout ),     .cout()); // synopsys translate_off defparam \add0~0 .lut_mask = 16'h55aa; defparam \add0~0 .sum_lutc_input = "datac"; // synopsys translate_on  assign c = \c~output_o ;  endmodule 

qsim output:

vsim -l cycloneive work.ca # vsim -l cycloneive work.ca  # loading work.ca # ** error: (vsim-10000) /home/bijan/project/quartus/ca5/simulation/modelsim/ca.vo(76): unresolved defparam reference '\c~output ' in \c~output .bus_hold. #         region: /ca # ** error: (vsim-10000) /home/bijan/project/quartus/ca5/simulation/modelsim/ca.vo(77): unresolved defparam reference '\c~output ' in \c~output .open_drain_output. #         region: /ca # ** error: (vsim-10000) /home/bijan/project/quartus/ca5/simulation/modelsim/ca.vo(86): unresolved defparam reference '\b~input ' in \b~input .bus_hold. #         region: /ca # ** error: (vsim-10000) /home/bijan/project/quartus/ca5/simulation/modelsim/ca.vo(87): unresolved defparam reference '\b~input ' in \b~input .simulate_z_as. #         region: /ca # ** error: (vsim-10000) /home/bijan/project/quartus/ca5/simulation/modelsim/ca.vo(96): unresolved defparam reference '\a~input ' in \a~input .bus_hold. #         region: /ca # ** error: (vsim-10000) /home/bijan/project/quartus/ca5/simulation/modelsim/ca.vo(97): unresolved defparam reference '\a~input ' in \a~input .simulate_z_as. #         region: /ca # ** error: (vsim-10000) /home/bijan/project/quartus/ca5/simulation/modelsim/ca.vo(113): unresolved defparam reference '\add0~0 ' in \add0~0 .lut_mask. #         region: /ca # ** error: (vsim-10000) /home/bijan/project/quartus/ca5/simulation/modelsim/ca.vo(114): unresolved defparam reference '\add0~0 ' in \add0~0 .sum_lutc_input. #         region: /ca 

add library devicename_ver in library tab in start simulation window sure use _ver (verilog) library otherwise see same error